Memory readout and summing system



June 22, 1965 H. FLEISHER ETAL 3,191,012

MEMORY READOUT AND SUMMING SYSTEM Filed Aug. 24. 1961 '7 Sheets-Sheet 1 562-4 3642 124 seo-4 0 0 0 F IG. FIG. 15 150 ATTORNEY June 22, 1965 H. FLEISHER ETAL MEMORY READOUT AND SUMMING SYSTEM Filed Aug. 24, 1961 '7 Sheets-Sheet 3 Ef; C 2* 5a-g F40 29 152 r 15o r1211 26 1m 5o 11111112 L 0' l 46h TVC-r 46u 46 52 56 46c N31 J 64 /27 60 48a "Lf :f 481 62 58 48C 4 92 6 REDf A] @L o 11 u 9Hl 44 MMT M56 /28 0 112 100\1 094 T21 52 r 0' T6 L l; 11a/f l. 02 l se 80/4 75 1 iiD- 9 0 as L L74 "1 106 so /u 154 12o 12e FI 25 f L H1 1227 |01/ l 116% 9a t FIG. 2G

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June 22, 1965 H.F1 E1SHER Em. 3,191,012

MEMORY READOUT AND SUMMING SYSTEM Filed Aug. 24. 1961 'T Sheets-Sheet 4 B c A 152\I 15o Lm F I G 2 b f *u *Tf-1 .0 I I# I 1111` I ,E0 I 161 111-1 1 PSI 1 1, 1 II 154 122 `\25 I 1 1 I l I 124 Vl I I 2 6 I I ,1, I 16-5 L 4 1s 5 I I if L41 I 9i I 8 8, E I I I 1 ,54 1 1 I u {LI- 25 I l T I I J 152 ,130 124 ,12a I 1 1. I

M11/ LJN 715-1/- 111-2 WORD f 1H MEMORY J6- F1621: 11s-5 BIT HJ11s-4 f REG1STER 1s 4 4111-5 11s-s June 22, 1965 H. FLElsHER ETAL, 3,191,012

MEMORY READOUT AND SUMMING SYSTEM FIG.4b

June 22, 1965 H. FLEISHER ETAL 3,191,012

MEMORY READOUT AND SUMMING SYSTEM Filed Aug. 24. 1961 7 Sheets-Sheet 7 V* *I 2o FIG.6o I I/ I I I I 554 r I I o C I I I I 549 I i f l i 5(45 I I I" B I 546 l i '545 lvr I I 124 20 EL 554 END 0F 550 F16. 6b -READouT 'f-549 I 548 clRcuIT \547 CYCLE I 1 IZIBIIsIGITIBI n PULSE swIrcH 56o a..'"PuLsEs swlTcHEs 562566510 c,c;c,c' PuLsEs swITcHI-:s 564,572, 514,516

United States Patent O MEMORY READOUT AND SUMMING SYSTEM Harold Fleisher, Poughkeepsie, and Robert I. Roth, Briarclilf Manor, N.Y., assignors to International Business Machines Corporation, New York, NX., a corporation of New York Filed Aug. 24, 1961, Ser. No. 133,679 9 Claims. (Cl. 23S-164) This invention relates to a memory readout system and more particularly to a system for reading out data parallel by bit to a summing circuit by repetitive groups of pulses.

This type of system is particularly adaptable to use with an associative memory system where particular fields of particular memory words are identified and binary 1 bits in these fields are to be read out to counters.

The closest known prior art is a system described in copending application Serial Number 120,213, led June 28, 1961 on behalf of H. Fleisher and R. I. Roth and assigned to the assignee of this invention. However, the system in the above cited application provides for serialby-Word, parallel-by-bit read out of selected Words wherein all words are compared simultaneously with an association word and indications of matches and mismatches are stored in a single column indicating circuit. Thereafter, read out pulses are applied to enable a single Word and each pulse applied to a bit position of that word flow out of the memory on a binary 1 line or a binary 0 line in accordance with the binary state of the particular bit position.

The present system is asynchronous in the sense that the read out is parallel-by-bit without regard to whether the binary data read out at a given time are in the same or different memory words. The readout signal applied to each column of memory iiows directly to the tirst bit position storing a binary 1 and reads the binary 1 out. The next read out pulse reads out the next following binary 1.

When the last binary 1 has been read from a particular column, which may either follow, precede or occur at the same time as the reading of the last binary l from other columns, the next following readout signal applied to that column ows to an associated carry register to readout a binary 1 carry value which may be stored therein. A plurality of carry registers associated with a column are read out in the same manner as the memory storage positions.

It is thus apparent that each readout signal applied to a memory column is effective to readout a binary 1 as long as one remains stored anywhere in the column.

The binary ls read out of memory are immediately entered into a summing register and summed with a binary value therein.

Accordingly, it is a primairy object of this invention to provide improved apparatus for parallel memory readout.

Another object of this invention is to provide an improved memory readout and adding system.

A further object of this invention is to provide an improved binary counter.

Yet another object of this invention is to provide an improved asynchronous system for extracting and summing data from a memory.

Another object of this invention is to provide an improved summing device adapted for delayed adding of carries.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

In the darwings:

FIGURE 1 shows the arrangement of FIGURES la and lb to form a circuit schematic.

FIGURES la and lb taken together form a circuit schematic of the novel system.

FIGURE 2a is a detailed showing of a bit register.

FIGURE 2b shows the operative relationship between plural bit registers.

FIGURE 2c shows a schematic representation of a column of bit registers illustrated in FIGURE 2b.

FIGURES 3a and 3b show schematic representations of cryogenic gate elements.

FIGURE 4a shows a detailed register.

FIGURE 4b shows a schematic representation of the sum register of FIGURE 4a.

FIGURE 5a. shows a detailed schematic of a carry register.

FIGURE 5b shows a schematic representation of the carry register of FIGURE 5a.

FIGURE 6a shows a detailed schematic of an end of readout circuit.

FIGURE 6b shows a schematic representation of the end of readout circuit of FIGURE 6a.

FIGURE 7 is a timing chart.

General Description schematic of a sum This system includes an n x m bit memory arranged in n word rows and m bit columns and register unit consisting of a sum register for each of the m columns plus suflicient registers to accommodate carries.

Each sum register except the highest order one is provided with a first order carry register in the next higher order column to receive carries from the associated sum register. First order carry registers are provided with second order carry registers; second order carry registers provided with third order carry registers; etc. The number of orders of carry registers depends upon the maximum number of carries which may be propagated and therefore upon the number of words in memory since all readout and adding of stored data in a column is accomplished before the carry registers in that column are interrogated for carries.

Readout signals are periodically applied at the top of each column. Each readout signal is effective to read out data stored in the first bit position as the signal tlows through the column from top to bottom.

A stored binary 1 is considered stored data whereas a stored binary 0 is considered as absence of stored data. After the data are read out of that bit position, the register is reset whereby the next applied readout signal will pass on to the next folliwing position which stores data.

After all stored data have been read out of a particular column of memory, the next applied readout -signal flows through that column of memory to the carry registers which are arranged in the column. 1n a manner similar to the readout of memory, the readout signal reads stored data from the tirst encountered carry register which contains stored data. The next readout signal is effective to read out the next following carry register data.

An end-of-readout indicato-r circuit is provided for each column of the system to indicate when all data have been read from the particular column of memory and associated carry registers. Asynchronously operating interrogation means are provided to detect when all end-of-readout circuits have been actuated after which the contents of the sum register unit may be read out.

Referring to FIGURES la and 1b, a system schematic is illustrated including a word memory and a counting circuit. The memory consists of four blocks designated word memory bit register and further designated 10A, lit-2, 1043 and 10-4, representing plural words of four binary bits each. While only four bit registers are shown, it will be understood that the system may consist of any suitable number of registers 10, depending upon the desired Word length. In the example described hereinfater, a tive word memory is assumed but it Will be understood that, in practice, the memory would consist of a larger number of words.

The counting circuit consists of sum registers or accumulators 1d, first carry registers 16, second carry registers 18, and end-of--readout check circuits 2?. The sum registers 14-l, 14-2, 14-3 and 14-4 correspond to the Word memory bit registers 10-1, lil-2, 1liand 1li-4. In addition, twvo sum registers herein designated 14-5 and 14-6 are provided for storing carry sums beyond the sum register 14-4.

A first order carry register 16-1 arranged in the second column from the right under ivoi'd memory bit register lil-2 is adapted to receive carries from sum register 14-1. A second order carry register 18-1 is arranged in the third column with the Word memory bit register 1u-3 to receive carries from carry register 16ml. Similarly, carry registers 16-2 and 18-2 are arranged to receive carries from sum register 14-2 and carry register 16-2 respectively. In a similar manner carry register 16-3 and 13-3 are provided as well as carry registers 16-4 and 16-5. End-ofreadout clzccl; circuits designated 2li-1, 2dr-2, 2&4, 2-4, 2li-5 and 2-6, one for each sum register 14, are provided.

lt will oe apparent how the expansion of tne four bit Words in memory will require additional units 14, 16, 13 and 29. While two orders of carry registers are sufficient for a five word memory, it will become apparent, as the description progresses, that a memory consisting of a larger number of Words will require additional orders of carry registers to store carries which are propagated from the lowest order carry registers. It will be apparent that the number of orders of carry registers may be expanded, to the extent required by the particular memory used, Without departing from the scope of this invention since all carry registers are identical and the interconnection of successive orders of carry registers is identical.

Binary l data bits in the word memory are read out, essentially parallel-'oy-bit, into the corresponding sum registers 14-1. to 14-4, and carries are propagated to the corresponding carry registers 16.

The read out is parailel-by-bit but without regard to whether the bits are in the same or different Words. In each bit position the first binary 1 encountered, reading from the top of the memory down, is read out by a rst group of readout pulses, the second binary 1 in each bit position is read out by a second group of readout pulses, etc. Assume, for example, that the four bit positions of the tive Words of memory contain the following binary bits.

Wor d The rst group of readout pulses reads out the binary ls in word lt'Wl), bit position 4(54), W1, B3; Wl, B2; W1, Bl. The second group of pulses reads out W5, B4; W2, B3', W2, B2; and W2, B1.

If a binary l is being read out from a word memory bit position in one column after all binary ls have been read out of another column, the readout pulse in the latter column will read a binary 1 carry from the corresponding carry register 18, if one is present, and if a binary l carry is not `stored there, will read a binary 1 carry from the corresponding carry register 16, if one is stored therein.

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Thus it is apparent that a readout pulse introduced into a particular bit column, including one or more of the components 1t), 16 and 18, will read out the first binary l stored in the memory 1l). In successive cycles after having read out all binary ls from the particular column word memory bit registers, the readout pulses 1vill then read out carries first from the carry register 18 and then from the carry register 16.

Before describing the circuit operation, a description is provided of the various blocks which are illustrated in FiGS. la and lb. Thereafter, the description or the circuit shown in FIGS. la and 1b will refer only to the block representations.

W on! memory Referring to FlG. 2n, a typical word memory bit register is illustrated. The register generally designated 25 includes a storage loop 26 which is defined by the points 26a, 261), 26C and 26d. The leg of the loop defined by points 26a, 26d is hereafter referred to as line 27. The leg defined by the points 26h, 26C is referred to as line 28. Current is supplied to the storage loop 26 through a terminal 29 at the top and exists through a terminal 30 at the bottom. Direct current applied to the terminal 29 remains on as long as the register 2S is in operation.

During a read operation current is applied to a ter minal 32 and flows along one of the vertical lines 34 or 36. Current on the line 36 represents a binary l. Current on the line 34 represents a binary 0. Current on the line 34 or 36 is supplied to a corresponding terminal 38 or 40 which may be connected to a load device (not shown). During a write operation, current is supplied to one of `the vertical lines 34 or 36 by ari input device (not shown) which may be connected to terminal 38 or 40.

Register 25 has a write line 42 and a read line 44. The write line 42 includes a control loop 46, and the read line 33 includes a sense loop 4S. Each ofthe foregoing loops is defined by points a, b, c and d associated with the loop number. The control Vloop 46 includes cryo trons Sil and 52. The storage loop 26 includes cryotrons 54 and 56. The sense loop 48 includes cryotrons 58 and 60, The line 34 includes a cryotrori 62 and the line 36 includes a cryotron 64. The foregoing gate elements have control windings as follows: gate 54, line 46a-46h; gate S6, line 46d-46c; gate 64, line 48u-4gb; gate 62, line 43d-48c; gate 50, line 34; gate 52, line 36; gate 58, line 27; gate 60, line 2S.

Referring to FIGURE 3a, a cryotron 66 is illustrated as having a contr-o1 winding 68 disposed about the cryotron gate element 70. While this cryotron is represented `as a conventional Wire wound cryotrori, it is to be understood that other types of cryotrions may be used. The circuit schematic of cryotron 66 in FIG. 3a is depicted in FIG. 3b in a simplified form. The same reference numerals employed in FIG. 3a are used in FIGURE 3b to designate corresponding parts. The simplified showing of FlG. 3b is employed in the various circuit schematics to represent a cryotron gate element.

The circuits of this invention are operated at low ternperatures such as by immersion in liquid helium. Current in the control winding 68 is employed to create a magnetic field which exceeds the critical field of the cryotron gate to drive the cry-otron resistive. When no current hows `in the control winding of the cryotron, the gate clement is superconductive and current lows therethrough.

information from an external device may be written into the register 25 or information stored in the register may be read to an external device. To illustrate a wiring` operation, assume that a binary 1 is to be written in register 25. First, the register is placed in the operative condition by applying direct current to terminal 29. This current remains on as long as the register remains in operation. Next, an information signal is supplied anchois to the vertical line 36. To store a binary 0 bit, current would be applied to line 34. Only one ofthe two lines is energized at any one time.

A current is applied next to :the write line 42. Cnrrent on the line 36 drives the gate 52 resistive. Consequently, current on the Write line 42 is diverted from that portion of the vcontrol loop 46 defined by the points 46-u, d, c and b, to that portion of the loop defined bythe points 46a and 461;. Current flowing in this leg of the loop drives the gate `54 resistive whereby current from the terminal 29 is diverted to the line 28. Current llowing in the line 28 is arbitrarily designated as representing a binary 1. Current tlowing in the line 27 is arbitrarily designated as representing ra binary 0. Thus, a binary l is writtten in the register 25. At this point, the current on fthe write line 42 may be terminated and the information signal represented by the current applied to the terminal may be terminated.

A binary 0 is stored by applying a current to line 34 instead of to line 36, thus driving the gate resistive whereby current in the loop 46 is diverted to that portion of the loop defined by the points 46a, 46d, 46c and 4617. Current in this leg of the loop 46 drives the gate 56 resistive whereby current from the terminal 29 is diverted to the linc 27.

To illustrate a read operation, assume that a binary l stored `in register 25 is to be read out. Current applied to the terminal 29 during the write operation remains on. Current is applied to the terminal 32 and to the read line 44. lit is permissible to energize the terminal 32 and the read line 44 simultaneously.

The current in the line 28 representing the stored binary 1 drives the gate 60 resistive, whereby current on the read line 44 is diverted through that portion of the control loop 48 defined by the points 43d and 48e. Current in this portion of the control loop drives the gate 62 resistive and diverts current from the terminal 32 to the vertical line 36. rPhe binary l read from register 25 is thus supplied to a utilizing `device via the terminal 40. At this point the current on the read line 44 and the terminal 32 may be terminated. The direct current signal applied to the terminal 29 is maintained.

lf a binary 0 is in the `register 25 when the currents are applied to terminal 32 and line 44, the gate 58 is resistive whereby the current applied to terminal 44 is diverted through that portion of the loop 48 defined by the points 43d 48u, 48h and 48C, thus driving the gate 64 resistive and diverting the current applied to terminal 32 through the binary 0 line 34 to the terminal 33.

For a more detailed description of this register, reference may be made to application Serial Number 30,019, filed May 18, 1960 and assigned to the assignee of this invention.

Referring again to FIG. 2a the register disclosed in application Serial Number 30,019 `and described hereinbefore is modified by the addition of a read loop 71 cornprising lines 72 and 74 connected in parallel in a line 76. The line 72 includes a cryotron gate S0 having as a control winding the line 28 of storage loop 26. The line 74 includes a cryotr-on gate 86 having as a control winding the line 27 of storage loop 26.

A pair of cryogenic flip-flops 88 and 90 form a part of the memory cell 25. The loop 71 links a pair of parallel connected lines 92 and 94 which form the ipop 88. The lines 92 and 94 are common connected through a line 96 to a source of direct current and through a line 98 to ground. The ground connection may be either direct or through a series of similar loops. The line 92 contains a cryotron gate element 100 having the line 72 for a control winding. The line 94 contains a cryotron gate element 102 which has the line 74 for a control winding. The line 92 also contains a cryotron gate element 104 and forms the control Winding for a gate clement 106. The line 94 forms the control winding for a cryotron gate element 108. The flip-tlop conalti D sists of parallel connected lines and 112 connected between a direct current power source and ground via lines 114 and 116, similar to the connection of tlip-flop 88. The line llt) includes a cryotron gate element 118. The line 112 includes a cryotron gate element 120 and forms a control winding for a gate element 122.

With a binary t) or a binary 1 stored in the loop 26, an input pulse on the line 76 is directed through either the line 72 or 74 in accordance with the binary State of the loop 26 and transfers the binary digit from the loop 26 to the loop 88 by rendering either the cryotron gate 100 or 102 resistive. With a binary 0 stored in the loop 26, current applied to the lines 76 flows through the line 72 and gate 80 rendering the gate element 100 resistive. Therefore, current applied to the line 96 flows in the line 94 rendering gate element 108 resistive, thus representing a binary 0 in Hip-Hop 88. With a binary l stored in the loop 26, current applied to the line 76 flows through the line 74 and gate 86 rendering the element 102 resistive and causing current representative of a binary l to flow in the line 92 rendering the gate clement 106 resistive.

The Word memory may be operated as an associative memory whereby data from memory register flip-flops 26 are transferred to the corresponding flip-flops 88 selectively in accordance with associative data. Since the association feature per se does not constitute a part of the present invention, the association circuitry is not illustrated. For the purposes of this invention, it is assumed that all binary ls in the memory registers are to be read out and added.

To read a binary digit from the flip-flop 88, a current hereinafter referred to as an A pulse is applied to a line 124. if the llip-tlop 88 stores a binary l, the current is in the line 92 and the gate element 106 is resistive whereby the A pulse cannot ilow through the gate clement 106 and continue on the line 124, but is diverted through a line 126 which forms the control winding for gate element 120, through the gate element 108, and through a line 128 to a counter.

If the iip-flop 88 stores a binary 0, the gate 10S is resistive and the A pulse tlows through the line 124, the gate element 106 and, via the line 124, to a next succeeding flip-flop 88 of another register to read out a binary 1 stored thercin.

Following the A pulse, a B pulse is applied to a line 132 to reset the flip-flop 88 to its binary 0 state. The B pulse on line 132 is diverted through a line 134. Since gate element is resistive, gate element 122 is superconductive. The pulse on line 134 Hows through gate 122 and renders the gate element 104 resistive thus resetting llip-op 88 to its binary 0 state by diverting current from the line 92 back to the line 94.

Following the B pulse, a C puise is applied in a line to reset the Hip-flop 90 to the 0 state. This C pulse renders cryotron `gate element 118 resistive to divert current on the line 110 back to the line 112.

Referring to FIGURE 2b, two bit registers 25 arel illustrated. The circuits are somewhat abbreviated from that shown in FIGURE 2a for clarity of illustration. The two bit registers are arranged one above the other to illustrate their interconnecting and the manner of applying A, B and C pulses thereto. The break line indicates omission of identical units. The assembly ncluding a plurality of registers 25 comprises a Word memory bit register 10. An A pulse on the line 124 is permitted to liow through the gate element 106, if the flip-flop 88 stores a binary 0, or is diverted to the line 126, if the flip-flop 88 contains a binary 1.

If diverted to the line 126, the pulse emerges on the line 128 Where it indicates the presence of a binary 1 in the tiip-llop 88. lf the A pulse is permitted to continue on line 124, it is directed in the next register 25 in accordance with the binary O or binary l state of the corresponding flip-flop 88. Thus it is seen that a column of bit registers may be interrogated by A pulses with each A pulse reading out the irst encountered binary 1 bit by passing on line 124 sequentially through registers storing binary Os until one is reached which contains a binary 1.

The B pulse on the line 132 is effective to reset the flip-flop S8 which has just had a binary l read therefrom. The ip-iiop 99 corresponding to the tlip-op 88 which has just had the binary 1 read therefrom is then in the binary 1 state, that is, current is owing in the line 110. Therefore, the B pulse on line 132 is diverted through the corresponding line 134 and through the superconductive gate element 122 to render the gate element 104 of hiphop S8 resistive thereby resetting the hip-liep 88 to its binary state. The current then lows to ground. The binary 0 state of other iiip-ops Qt) prevents the B pulse from flowing on other lines 134 and resetting to O the flip-flops 8S which have not yet been read out.

FIGURE 2c is a block schematic representation of a column of Word memory bit registers 25. This block, designated 1G, represents a column of registers of the type iilustrated in FIGURES 2a and 2b, in this instance, ve successive bit registers corresponding to words 1, 2, 3, 4 and 5. Five input lines 76-1 through 76-5 are shown entering the block on the right and emerging on the left. The A pulse is shown entering at the top on line 124 and exiting at the bottom on line 124 or line 12S. The B pulse is shown entering at the top on line 132 and exiting at the bottom. The C pulse is shown entering at the top on iine 13! and exiting at the bottom. .he word bit registers do not per se comprise a part of the present invention and therefore are illustrated in FGS. la and 1b by the diagrammatic representation of FIGURE 2c.

Sum register Referring to FIGURE 4a, a schematic representation of a typical sum register 141 is shown. Each sum register is divided into three sections designated a, b and c, for example, register 14-1 consists of sections 14-1a, 14-1b and 141c. The sum register includes three tlipfiops designated 150a, 156i) and 150e corresponding to the sections a, b, and C. Each flip-flop consists of a pair of parallel connected lines similar to those described in the word bit registers hereinber'ore. The current in the left hand line represents the storage of a binary 1, whereas current in the right hand line represents storage of a binary t). A binary 1 count is first entered in a sum register hip-op 150b by an A pulse on the line 128 from a corresponding word bit register 1t) or from a carry register 16 or 18. This pulse renders a cryotron gate element 152 resistive thereby diverting current on a line 154 from the line 156 to the line 158. The flip-flop 150b is later reset to its binary 0 state by a C pulse on a line 160. The pulse on the line 16h renders a cryotron gate element 162 resistive thus diverting current back to the line 156. The C" pulses are coincident with the previously described C pulses (see the timing chart, FIG. 7).

A binary 1 is stored in the flip-flop 150e by rendering a gate element 164 resistive, whereas a binary 0 is stored therein by rendering a gate element 166 resistive. The binary contents of hip-flops 156e and 159i are added together by an adding tree consisting of cryotron gate elements 168, 170, 172, 174, 176 and 178. The binary sum of flip-flops 150a and 150b is stored in cryotron gate elements 180, 182 and 184 of flip-Hop 159C. The contents of the flip-flop 150e are transferred to ilip-iiop 15% by a C' pulse on a line 183. The C pulse emerges from the sum register on a line 186.

The contents of the sum register, as stored in the flipflop 150:1, are read out on lines 189 and 192 by a B" pulse applied to a line 193. An output on the line 192 is indicative of a binary 0, Whereas an output on the line 189 is indicative of a binary 1.

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With a binary value, for example, a binary 1 stored in flip-Hop th:, and a binary 1 stored in hip-flop 15b by an A pulse on the line 123, a B' pulse applied to a line 194 is directed by the resistive state of gate element 193 from the line 200 to the line 262, through the gate element 204 and through the control windings of the gate elements 178 and 174, thus rendering the latter two gates resistive. Similarly, a B' pulse on the line 196 is directed by the resistive state of gate element 206 (binary 1) from the line S to the line 210 and through gate element 212, thus rendering the gate element 170 resistive. The B pulse continues on line 214 to the top of the adding tree. Thus, with a binary 1 in dip-hop 150e and a binary 1 in flip-Hop 150k, the gate elements 170, 174 and 178 are resistive Whereas the gate elements 168, 172 and 176 are superconductive.

The B pulse on line 214 therefore flows through lines 216 and 218, rendering the cryotron gate 182 resistive. The resistive state of gate 182 causes current to flow in the right hand leg of ip-flop 150e to represent the storage of a binary 0. This is correct since the binary 1 of llip-ilop 150a added to the binary l of iip-op 150b results in a binary 0 sum with a binary 1 carry. The binary 0 is stored in hip-flop 150C and the binary 1 carry flows out on the line 229.

A binary 1 in dipdlop 15de and a binary 0 in flip-flop 15%, or a binary 0 in iiip-ilop 15G@ and a binary 1 in tlip`flop 150b causes the current to emerge from the adding tree on the line 222 to write a binary 1 in fliptiop 150e by rendering gate 184 resistive and to emerge on a line 224 which is the equivalent of a binary 0 or no carry. A binary 0 in flip-Hop 15de and a binary 0 in tiip-itop 15017 causes the current from line 214 to iiow through lines 226 and 228 to Write a binary 0 in the hipflop 150C and emerge on the t) carry line 224.

Thus the function of the sum register is to enter a binary count in the flip-flop 156i), add that count t0 the contents of tlip-ilop 150e, to store the sum in flip-hop 150e and to transfer the appropriate carry, 0 or 1, to the appropriate first carry register 16. Thereafter the contents of flip-op 150e are transferred to flip-hop 150a by a C pulse applied to line 183 preparatory to adding the next count. A C' pulse on line 183 is directed to the line by the binary 0 state of dip-Hop 150e as represented by the resistive state of gate element 191, and to the line 184 by the binary 1 state of dip-liep 150C, as represented by the resistive state of gate element 190, to store a corresponding binary value in gate elements 164 and 166 of flip-dop 150e. The C' pulse then emerges from the line 186. Current is introduced into the fliptlops 159e, 150i) and 150e through a line 230 and emerges on aline 232 from which it is fed either directly or through other circuits to ground.

Referring to FIGURE 4b, a block representation is shown of the sum register illustrated in detail in FIGURE 4a. This representation of FIGURE 4b is utilized in FIGURES la and 1b.

Carry register Referring to FIGURE 5cl, a circuit schematic illustrative of the carry registers 16 and 1S is shown. In the following description reference will be made to a carry register 16-1 but it will be understood that the same description applies to all carry registers 16 and 18. The register 16-1 is divided into three Sections, 16-151, 16-1b and 16-1c. The section 16-1a includes a flip-hop 240e: and a Hip-flop 242. The section 16-1b includes a Hipflop 240b and the section 16-1c includes a Hip-flop 24de. Each tiip-op is adapted to store a binary value, a binary 1 being represented by current in the left hand leg of the dip-flop and a binary 0 being represented by current in the right hand leg of the Hip-Hop.

In a manner similar to that described with reference to the sum registers in FIGURE 4a, a value is entered in iip-fiop 24019 and, by an adding tree including gate elements 244, 246, 248, 250, 252 and 253, the values in flip-flops 240g and 240b are added and the surn is stored in gate elements 254, 255 and 256 of flip-flop 240e. Thereafter, the contents of flip-flop 240eare transferred by a transfer pulse (C') on line 257, gate elements 258 and 260, and lines 262 and 264 to gate elements 266 and 268 of flip-liep 24011. The current then emerges from the carry register on a line 271.

Binary Os and binary ls are entered in flip-flop 240b by B pulses on lines 270 and 272 respectively. A binary representing current on the line 270 renders gate element 274 resistive whereas a binary 1 representing input on line 272 renders gate element 276 resistive. With binary values entered in flip-flops 240a and 240]), a B pulse applied to a line 280 conditions the gate elements 248, 250, 252 and 254 of the adding tree in accordance with the binary value in flip-Hop 24|lb. The B pulse applied to the line 282 conditions the gate elements 244 and 246 of the adding tree in accordance with the value in ip-op 24041. The B pulse thereafter is applied to either line 270 or 272 in accordance with Whether a binary 0 or binary 1 carry is being propagated. The input on line 270 or 272 may alter the conditioning of the adding tree by changing the value in the Hip-hop 240i). The B pulse then Hows through the adding tree and, in the manner described with reference to the sum registers, enters the sum of registers 240e and 240b in register 240e and produces the proper 0 or 1 carry on line 284 or 286 respectively. By reference to FIGS. 1a and 1b and the subsequent description thereof, it is apparent that the B pulse inputs to lines 280, 282 and 270 (272) are actually the same pulse directed through devious paths.

In a manner similar to that described with respect to the word memory, bit register 1i), an A pulse applied to the line 124 (which actually extends from a register 16) con tinues through the carry register 16 on the line 124 if the Hip-nop 24051 stores a binary O. If the flip-flop 24hr: contains a binary 1, the A pulse is diverted through a line 291 forming the control winding for a gate clement 294 in flip-hop 242 and through gate element 296 of flip-flop 24911 and a line 292 to the line 128 (see FIG. 1a and 1b).

The current in line 291 renders gate element 294 resistive diverting current from the right hand leg of dip-liep 242 to the left hand ieg and making gate clement 392 superconductive.

Following the A pulse, a B pulse applied to the line 132 flows through the gate element 302 and the control winding of gate element 304 of lip-ilop 240:1 to reset the flip-liep 246e to its binary 0 state. A C pulse applied to line 130 extending from a word memory bit register 19 Hows through gate element 368 of Hip-Hop 242 to reset this tlip-tlop to its 0 state.

Direct current is applied to the ip-ops 249e, 240i: `and 24de through a line 31! and flows to ground through a line 312. Current is applied to iiip-iiop 242 through a line 314 and ows to ground through a line 316.

Referring to FIGURE 5b, a block representative of the circuit shown in FIGURE 5r: is illustrated. This block representation is utilized in FIGURES 1a and 1b. Identical blocks represent carry registers 16 and 18.

End of readout circuit Referring to FIGURE 6a, an end-ofreadout circuit 20 is illustrated. The circuit includes a flip-Hop 320 adapted to store binary 0 and binary 1 representations. Current in the left hand line 322 represents a binary 1 and current in the right hand line 324 represents a binary 0. An A pulse applied on line 124 renders a cryotron gate element 328 resistive thus diverting current from a line 33t! to the line 322 to represent a binary 1. Current applied to the line 33t) ows through a line 332 to ground. A C pulse on a line 334 renders gate element 336 resistive, thus diverting current back to the line 324 to represent a binary 0. The line 324 forms the control winding for gate 10 elements 338 to 343. The gate elements 338 to 343 are connected in lines 345 to respectively.

An end-otrcadent circuit 20 is connected in each column or elements as shown in FIGURES la and 1b and is operative to indicate when all binary l bits in the corresponding column of word memory and all carries in registers 16 and 18 of the associated column have been added into the sum registers. When all such binary ls have been added, the next succeeding A pulse on line 124 switches the tlip-tlop 329 to the binary l state. After each A pulse, i3' pulses are applied to the lines 345 to 350 to readout the contents of the sum registers, provided that all binary ls in all columns have been added. A C' pulse is applied to the line 3.34 following the B' pulses to reset any tlip-llop 320 to the binary 0 state.

When all end-of-rcadout circuits are binary l) at the end of a given A pulse time, the following B pulses are permitted to pass through all end-of-readout circuits 29 on line 34S to 35i) to the lines 193 of associated sum registers to readout the contents of the registers.

actuated (set to Pulse generator This system is operated by repetitive sequences of pulses variously designated A, B, C, B', C', B, C, C'. It is well known that pulse generators may be constructed to provide any desired sequence ot pulses and therefore such a generator is not shown or described herein. Since the means for generating the pulses do not in themselves constitute invention, the sources of the various pulses, for cor1- venience ol illustration, are shown schematically as switches which are referred to as being opened and closed to produce the desired pulses.

Circuit description Referring to FGURES la and 1b, a block representation of the system is shown utilizing the block diagrams shown in FGURES 2c, 4b, 5b and 6b.

The system is operated by a series of pulses designated A, B and C which are entered into the word memory bit registers 1li-1 to 10-4 and into carry registers 18-3 and 16-5. Bach or" the pulses A, B and C is a direct current (D.C.) pulse and in each case the current source is represented by a terminal labelled with a plus (-1-) sign. The A pulses are applied to the various memory registers 10 and to the carry registers 18-3 and 16-5 through switches designated 3613-1 to S68-6. The B pulses are applied through switches designated 362-1 to 362-6. The C pulses are applied through switches designated 364-1 to 364-6.

B pulses are applied, coincidently with the B pulses, to the lines 194 of the sum `registers 14 (see timing chart FIG. 7). These B pulses originate at terminals labelled plus (l) and are connected to the lines 194 through switches designated 366-1 to 366-6. B pulses are applied, coincidently with the B and B pulses, through switches 370-1 to 370-6 to the lines 345 to 350 leading into the end-of-readout circuit Ztl-1.

C' pulses are applied, coincidently with the C pulses, through switches designated 372-1 to 372-6 to the lines 133 of the sum registers 14-1 to 14-6. A C pulse is applied, coincident with the C and C pulses, through a switch 374 to the line of sum register 14-1. A C" pulse is applied, coincidently with the C, C' and C" pulses through a switch 376 to the line 334 leading into the endo-readout circuit Ztl-1. The foregoing pulses as well as other inputs to the circuit are illustrated in the timing chart, FGURE 7.

In accordance with the earlier example, Word 1 of the memory is assumed to contain the binary number 15 (1111), words 2, 3 and 4 the binary number 7 (0111), and word 5 the binary number 9 (1G01). The carry registers 16 and 18, the end-of-readout circuits 20 and the sum registers 14 are assumed to be initially reset to t). Current is applied from terminals designated plus (-1-) through switches designated 378-1 to 373-5 to the lines lll 76-1 to i6-5 threading the word rucrnory bit registers 10. ln the 'manner described liereiribcore, the currents on the lines 76 transfer thc contents of the ip-iiops 26 to the corresponding ip-lcps A pulses are applied through the switches 36h-1 to 3513-6 and are effective, in the manner described, to apply a pulse to cach of the lines 1215 leading from the word 1 bit positions 1, 2, 3 and 4, since cach bit position contains a binary 1. A pulses applied through switches 3623-5 and 363-6 proceed, in the described manner through the lines 124 to the end-of-readout circuits 2li-5 and 2li-6. The circuits 2li-5 and itil-6 are thus set to their binary l states. The currents on lines 12S-1 to 12S-4 store binary ls in the corresponding sum register sections 14s-1b, lll-2b, 14-3b and 14e-Sib.

The B, B and B" pulses are then applied through their respective switches. The B pulses applied through switches 362 reset the bit registers of word l to the binary 0 state. The B pulses applied through switches 362-5 and 362-6 are ineffective since the carry registers 18-3 and 16-5 are already in their binary 0 states. The B" pulses applied through switches 3711-1 to 376-6 interrogato the six end-of-readout circuits 20 but are ineffective since circuits 2li-1 to 26-4 are in their binary 0 states and the currents applied through the switches 37h are blocked.

The B pulses applied through the switches 366-1 to 366-6 add the binary contents of sum register b sections to the binary contents of the corresponding n sections. Referring, for example, to the register 14-1, the B' pulse applied through the switch 366-1 iiows through line 194 into the register section 14-1b, through the line 195 to to the line 279 to carry register 16-1., through the output line 280 of register 16-1 and the input line 279 of register 18-1, through the lines 283, 282 and 283 of the register 18-1, through lines 282 and 233 of register 16-1 and lino 196 of surn register 14-1. The B pulse then tlows through the adding tree of register 14-1 to add the binary 0 in section lil-la to the binary l in section 14-115 and store the binary 1 sum in register 14E-1c. A binary 0 carry pulse emerges from register 14-1 on the line 224 and is applied to the line 27% of carry register 16-1. This B pulse ilows through the adding tree of register 16-1 to add the binary (l in section 1i6-1a; to the binary O in section 16-1b and store the binary (l sum in section 16-1. The B pulse emerges from register 16-1 on the binary 0 carry line 2li-l and is applied t0 the line 270 of carry register 18--1 where it similarly adds the binary Os in sections 18-1a and 1li-1b and stores the binary 0 surn in 1li-1c. The current emerges on the binary 0 carry line 284 and flows to ground. The B' pulses applied through switches 366-2 to 366-4 accomplish the foregoing function in exactly the same manner. The B pulses applied through switches 366-5 and 366-6 are inelfective since they are operating on empty registers. Hereinafter reference to ls and O's will be understood to mean binary ls and binary Ds.

The C, C', C" and C" pulses are then applied. The C pulses applied through the switches 364-1 to 364-4 are effective to reset the flip-hops 9G in word 1 bit positions 1, 2, 3 and 4 to their 0 states, since each was set to the 1 state when the binary 1 was read therefrom. The C pulses applied through switches 364-5 and 364-6 are inetective since the corresponding flip-hops 242 in carry registers 18-3 and 16-5 were not set to the 1 condition.

The C" pulse applied through the switch 374 flows through the b sections of all sum registers 14 and resets to the 0 state those registers which contained a 1, in this case registers li-lb, 1li-2b, 14--3b and 14-411. The C'" pulse applied through the switch 376 resets the end-of-readout circuits 2li-5 and Ztl-6 to their 0 states. The registers 2li-1 through Ztl-4 were already in their 0 states.

The C pulses applied through the switches 372-1 to 372-6 are effective to transfer the contents oi the c sections of the sum registers 14, carry registers 16 and carry registers 18 to the u sections thereof. For example, the C pulse applied through the switch 372-1 flows through the line 183 into the sections 14-10 and transfers the l stored therein to the section 14-1a. The C pulse then flows through the line 186 and the line 257 into the register section 16-1c. Since the section 16-1c contains a 0, a 0 is written in section 16-1a and the C pulse emerges on the line 271. The C pulse continues through the line 257 into carry register 18-1 where it writes a 0 in section 18-1a. This pulse then tlows through thc line 271 to ground. In a similar manner the 1s in surn register sections 214-20, 14-3c and 1li-4c are transferred to the corresponding register sections 1li-2u, llt-3a. and 1li-4a.

This is the end yof a first adding cycle. A second adding cycle is commenced by again closing the switches 366-1 to 369-6 to apply A pulses to the corresponding lines 124. The A pulses enter ls in the surn register sections 1f-1b, 11i-2b, 1li-3b and 14-4b via corresponding lines 128. The ls read out are those from W5, B4; V'JZ, B3; W2, B2; W2, B1. The A pulses applied to switches 360-5 and S60-6 flow into the corresponding endof-readout circuit 26-5 and 2li-6, setting these circuits to their l states.

The B" pulses are applied during each adding cycle to the switches 370 and are ineffective during each cycle until all adding of ls from memory and carries from the carry registers is complete. Therefore, further reference will not be made to the B pulses until this end of adding condition is achieved. Similarly, reference to the C'" pulses will not be made since a C'" pulse is applied during each adding cycle to reset to 0 any circuits 2G which have been set to their 1 state. Similarly, reference will not be made to the C" pulses which are applied each adding cycle to reset the sections o or" all sum registers 14 to the 0 state.

Following the A pulses in the second adding cycle, the B' pulse applied through switch 366-1 follows the previously described path and is effective to add the l in section 14-1a to the 1 in section i4-1b storing the 0 sum in section 14-1c and propagating a 1 carry on line 220 to section 16-119 of carry register 16--1. This same B pulse is effective to add the 0 in section 1li-1a to the 1 in 16-1b, storing the 1 sum in section 1li-1c and propagating a 0 carry to the carry register 18--1. The carry register 18-1 remains set at 0.

Similarly, the B pulse applied to switch 366-2 adds the l in section 11i-2n to the 1 in section 14-2b storing the 0 sum in section 14-2c and entering the 1 carry in section 16-2b of register 16-2. This same B' pulse adds the O in section 16-2a to the l in section 16-2b and stores the 1 sum in section 16-2c. The t) carry to register 18-2 leaves this register set to O.

The effect of the B pulses applied through switches 366-3 and 366-4 is identical to the foregoing description of the B pulses applied to switches 366-1 and 366-2. The B pulses applied to switches 366-4 and 366-5 are ineffective due to the 0 contents of the associated registers.

The C' pulses applied to the switches 372-1 through 372-6 are effective to transfer the contents of all c" sections of sum registers and carry registers to the corresponding a sections. At this point in the operation, carry registers 16-1, 16-2, 16-3 and 16-4 store ls. All other registers store Os.

A third adding cycle is initiated by again closing switches 360-1 to S60-6. In this adding cycle the only remaining ls in the memory 10 are in bit positions 1, 2, and 3. The ls from W3, B3; W3, B2 and W3, B1 are entered into register sections At4-3b, 14-20 and 14-111 respectively. The A pulse through switch 360-4 ows through the associated line 124, and through a carry register 18-2 to readout the 1 in register 16-3 and enter it in register section 1li-5b. Similarly, the A pulse through switch S60-S reads the 1 from register 16-4 to register 13 section 14-5b. The A pulse through switch 3661-6 turns on the end-ofreadout circuit 213-6. The following B pulses reset the W3, B3; W3, B2; and W3, B1 Hip-ops 88 and the Hip-flops 240a of registers 16-3 and 16-4.

The B' pulse applied through the switch 366-1 adds the 0 in section 14-1a to the 1 in section 14-1b and stores the 1 sum in section 14-1c. The 0 carry on the line 224 is applied to section 16-1b of register 16-1. This carry is added to the l in section 164e, and the 1 sum is stored in the section 16-1c. The 0 carry to register 18-1 leaves this register set at 0.

The B' pulse applied through switch 366-2 similarly adds the O and 1 in sections 14-2a and 14-2b and enters the l sum in section 14-2c. The 0 carry to section 16-2 is added to the l in section 16-2a and the 1 sum is stored in section 16-20. The 0 carry to register 18-2 leaves this register set at 0. The B' pulse applied through switch 366-3 adds the 0 in register 14-3a to the l in register 14-3b storing the l sum in section 14-3c and propagating a 0 carry to register 16-3. This 0 carry is added to the 0 in section 16-3a and the 0 sum is stored in the section 16-3c. The 0 carry to register 18-3 leaves this register set at 0. The B pulse applied to register 14-4 adds the 1 in section Irl-4b to the 0 in section 14-4rl, storing the 1 sum in section 14-4c and propagating a 0 carry to register 16-4 where it is added to the 0 in section 16-4a. The B' pulse applied to register 14-5 adds `the l in section 14-5b to the 0 in section 14-5a, storing the sum in section M-Sc and propagating a 0 carry to register 16-5. The B pulse to register 14-6 is ineffective due to the 0 contents of the associated registers.

The C pulses applied to switches 372 transfer the contents of all c sections of registers 14, 16 and 1S to the corresponding "a sections. At this point, registers 14-1, 14-2, 14-3, 14-4, 14-5, 16-1 and 16-2 store ls. All other registers store Os.

A fourth adding cycle is initiated by closing the switches 360-1 to 360-6. The A pulses read ls from W3, B3; W3, B2 and W3, Bl. The A pulses through switches 360-4, 360-5 and 366-6 are effective only to turn ON the corresponding end-of-readout circuits 20. The ls in carry registers 16-1 and 16-2 are not read out since the associated A pulses are utilized to read ls from memory.

The B pulse applied through switch 366-1 adds the 1 in register section 14-1b to the 1 in section 14-1a storing the 0 sum in section 14-1c` and propagating a 1 carry to register 16-1. This same pulse adds the l in section 16-1b to the l in section 16-1a storing the t) sum in section 1li-1C and propagating a 1 carry to register 18-1. The B pulse applied to switch 366-2 adds the l in section 14-2a to the 1 and section 14-2b storing the 0 sum in section 14-2c and propagating a 1 carry to register 16-2. The ls in register sections 16-2a and 16-221I are adde The 0 sum is stored in section 16-20 and the 1 carry is propagated to register 18-2.

The B pulse applied through switch 366-3 adds the 1 in section 14-3b to the 1 in section 14-3a storing the 0 sum in section 14-3c and propagating a 1 carry to register 16-3 where it is added to the 0 in section 16-3a. The 1 sum is entered into section 16-3c and a O carry is propagated to register 18-3.

The B' pulse applied to registers 14-4 and 14-5 add the ls in the respective sections "a to the Os in respec tive sections b, storing the 1 sums in respective sections a The B pulse to register 14-6 is ineffective due to the binary 0 contents of that register.

Again the C pulses transfer the contents of the c sections of registers 14, 16 and 18 to the corresponding "a sections. At this point only registers 14-4, 14-5, 16-3, 18-1 and 18-2 store ls A fifth adding cycle is initiated during which a 1 is entered from word tive bit position l into register section 14-1b. A 1 is read from carry register 18-1 into register section 14-3b. A 1 is read from carry register 18-2 into 14 section 14-4b. Register sections 14-2b, 14-5b and 14-6b remain set at 0.

The B pulse applied to register 14-1 adds the 0 in section 14-1a to the 1 in section 14-1b entering the l sum in section 14-1c and propagating a 0 to carry to register 16-1. The B pulse to register 14-3 similarly enters the 1 sum in section 14-3c and propagates a 0 carry which is added to the 1 in register 16-3. The B' pulse to register 14-4 adds the ls in sections a and b entering the 0 sum in section 14-46 and propagating a 1 carry to register 16-4. The B pulse to register 14-5 adds the 1 in section 11i-5a to the 0 in section III-5b enter in the l sum in section 14-5c and propagating a 0 carry to section 16-5. At this point only registers 14-1, 14-3, 14-5, 16-3 and f 16-4 contain ls.

All ls from word memory 1t? have now been read out to the adding circuits. The A pulses applied to switches 360 in a sixth adding cycle are effective to read the 1 carries from carry registers 16-3 and 16-4. The A pulses applied to switches S60-4 and 360-5 transfer the ls from register 16-3 and 16-4 to register sections 14-4b and 1- 5b. The B pulse adds the 0 in section 14-4a to the 1 in section 14-415, storing the l sum in section 14-4c and propagating a 0 carry to register 16-4. The B' pulse to register 14-5 adds the two ls, entering the 0 sum in section 14-56 and propagating a 1 carry to register 16-5. At the end of this sixth adding cycle, registers 14-1, 14-3, 14-4 and 16-5 contain ls.

A seventh adding cycle is initiated to transfer the 1 carry from register 16-5 to register 14-6. This completes the adding operation and, during the next adding cycle, all A pulses flow directly to the associated end-of-readout circuits 2t) setting all of them to their 1 states and permitting the B pulses applied to switches 370-1 to 370-6 to How through the lines 345-359 and the lines 193 of the sum registers 14, to read out the contents of these registers on lines 189 and 192. At this point the registers 14-1, 14-3, 14-4 and 14-6 contain ls which represent a sum of 45.

As stated hereinbefore, in a large memory, additional orders of carry registers beyond registers beyond registers 18 will be required to store carries, since a carry is not read out of a carry register until all ls in the corresponding column of memory have been read out. However, the addition of these other carry registers is merely an extension of the counter disclosed herein. For example, the first order counter includes the sum register 14-1, carry register 16-1 and carry register 13-1. It iS a simple matter to extend this counter to include any number of additional carry registers identical to the registers 16-1 and 18-1 and interconnected in the same manner. A variation of this counter system consists of passing the pulses A, B and C through the carry registers 16 before passing them through the word memory. In this instance, the second order of carry registers 13 is not required since a 1 carry in a register 16 is read out by the next A pulse following the B pulse which stored the carry in the register 16. Each time a l carry is entered in a register 16, it is read out in the next adding cycle in preference to a 1 from the corresponding column of word memory. This reduction in carry registers is ol'iset by a sacrifice in speed since the immediate reading out of each carry delays the reading out of memory data. For example, with this variation, the addition of 128 ls in the low order position requires 64 adding cycles for reading the carries from register 16-1 plus a cycle for each 1 stored in the second order column of memory. Using the multiple orders of carry registers, the 64 carries would be represented by a single l in a seventh order carry register which would be read out in a single cycle as compared with the aforementioned 64 cycles.

While the invention has been particularly shown and described with reference to preferred embodiments there of, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A memory readout system comprising, in combination, a memory consisting of rz m storage means arranged in n word rows and m bit columns, each said storage means scttable selectively to opposite binary states, readout means associated with each said storage means and operable by a readout signal applied thereto to produce an output signal on a tirst output line when the correspond- 'ig said storage means is in one binary state and on a second output line when the corresponding said storage means is in the opposite binary state and means connecting said readout means of each said storage means, after the rst said storage means in each said column, to said first output line of the preceding storage means in the same column.

2. A memory readout system comprising, in combination, a memory consisting of n m binary bit registers arranged in n word rows and m bit columns, binary storage means associated with each said register and settablc to the binary state of the associated register, readout means associated with each said storage means and operable by a readout signal applied thereto to produce an output signal on a first output line when the corresponding said storage means is in one binary state and on a second output line when the corresponding said storage means is in the opposite binary state and means connecting said readout means of each said storage means, after the first said storage means in each column, to said rst output line of the preceding storage means in the same column.

3. A memory readout system comprising, in combination, a memory consisting of n m storage means arranged in n word rows and m bit columns, each said storage means settable selectively to opposite binary states, readout means associated with each said storage means and operable by a readout signal applied thereto to produce an output signal on a first output line when the corresponding said storage means is in one binary state and on a second output line when the corresponding said storage means is in the opposite binary state, means counecting said readout means or each said storage means, citer the iirst said storage means in each column, to said first output line o the preceding storage means in the same column, and reset means associated with each said storage means and operable by a reset signal applied thereto to set the corresponding said storage means to said one state whereby a succeeding said readout signal is applied to said readout means of the next succeeding said register.

d. A memory readout system comprising, in combination, a memory consisting of 11 m storage means arranged in n word rows and m bit columns each said means settable selectively to opposite binary states, readout means associated with each said storage means and operable by a readout signal applied thereto to produce an output signal on a iirst output line when the corresponding said storage means is in one binary state and on a second output line when the corresponding said storage means is in the opposite binary state, means connecting said readout means of each said storage means, after the first said storage means in each column, to said first output line of the preceding storage means in the same column, first reset means associated with each said storage means and operable by a reset signal applied thereto to set the corresponding said storage means to said one state, second reset means associated with each said storage means settable to one binary state by an output signal on the corresponding said second output line and operable in said one state to permit said first reset means to reset the corresponding said storage means, and third reset means associated with each said storage means operable by reset signal applied thereto to set the associated said second reset means to its opposite binary state.

5. A memory readout and adding system comprising, in combination a memory consisting ot" nXm storage means arranged in n word rows and m bit columns and settable selectively to opposite binary states, readout means associated with each said storage means and operable by a readout signal applied thereto to produce an output signal on a first output line when the corresponding said storage means is in one binary state and on a second output line when the corresponding said storage means is in the opposite binary state, means connecting said readout means of each said storage means after the iirst storage means in each said column to said rst output line of the preceding storage means in the same column, an m order binary accumulator arranged in said m columns, means common connecting said second output lines of all said storage means in each column to input means of a corresponding order or said accumlator whereby each signal on said common connecting means enters a count in said corresponding order of said accumulator.

6. The invention of claim S including means for asynchronously reading out the contents of said m order accumulator when addition therein is complete.

7. A memory readout and adding system comprising, in combination, a memory consisting of rzxm storage means arranged in n word rows and m bit columns and settable selectively to opposite binary states, readout means associated with each said storage means and operable by a readout signal applied thereto to produce an output signal on a tiret output line when tbe corresponding said storage means is in one binary state and on a second output line when the corresponding said storage means is in the opposite binary state, means connecting said readout means of each said storage means after the rst storage means in each said column to said first output line of the preceding storage means in the same column, an m order binary accumulator arranged in said m columns, each said order operable to store a first binary digit in a first storage element, to receive .a second binary cigit in a second storage element, to add said first and second binary digits storing the binary sum in a third storage element and propagating a binary digit carry in accordance with said sum, means common connecting said second output lines of all said storage means in each column to an input terminal of said second storage element of a corresponding order of said accumulator whereby each signal on said common connecting means enters a count in said corresponding order of said accumulator.

8. A memory readout and adding system comprising, in combination, a memory consisting of n m storage means arranged in u word rows and m bit columns and settablc selectively to opposite binary states, readout means associated with each said storage means and operable by a readout signal applied thereto to produce an output signal on a first output line when the corresponding said storage means is in one binary state and on a second output line when the corresponding said storage means is in the opposite binary state, means connecting said readout means of each said storage means after the first storage means in each said column to said iirst output line of the preceding storage means in the same column, an m order binary accumulator arranged in said m columns, each said order operable to store a lirst binary digit in a tirst storage element, to receive a second binary digit in a second storage elment, to add said iirst and second binary digits storing the binary sum in a third storage element and propagating a binary digit carry in accordance with said sum, means common connecting said second output lines of all said storage means in each said column to an input terminal of said second storage element of a corresponding order ot said accumulator whereby each signal on said common connecting means enters a count in the corresponding order of said accumulator, binary carry registers corresponding to each order of said accumulator, each said carry register arranged in a said column corresponding to the next higher order from the associated said accumulator, readout means associated with each said carry register and operable by a readout signal applied thereto to produce an output signal on a first outline line when the carry register is in one binary state and on a second output line When the carry register is in the opposite binary state, means connecting said readout means of each said carry register to said first output line of the mth Said storage means in the corresponding said column and means connecting said second output line of each said carry register to the said common connecting means of the corresponding said column.

9. The invention of claim 8 including means for asynchronously reading out the contents of said m order accumulator when addition of data from said memory and said carry registers is complete.

References Cited by the Examiner FOREIGN PATENTS 7/60 Great Britain.

OTHER REFERENCES Pages 4-22, P23 and 2-22a to 4-23a, 2/4-7, Progress l0 Report on EDVAC, vol. 2, University of Pennsylvania.

MALCOLM A. MORRISON, Primary Examiner. WALTER W. BURNS, JR., Examiner. 

8. A MEMORY READOUT AND ADDING SYSTEM COMPRISING, IN COMBINATION, A MEMORY CONSISTING OF NXM STORAGE MEANS ARRANGED IN N WORD ROWS AND M BIT COLUMNS AND SETTABLE SELECTIVELY TO OPPOSITE BINARY STATES, READOUT MEANS ASSOCIATED WITH EACH SAID STORAGE MEANS AND OPERABLE BY A READOUT SIGNAL APPLIED THERETO TO PRODUCE AN OUTPUT SIGNAL ON A FIRST OUTPUT LINE WHEN THE CORRESPONDING SAID STORAGE MEANS IS IN ONE BINARY STATE AND ON A SECOND OUTPUT LINE WHEN THE CORRESPONDING SAID STORAGE MEANS IS IN THE OPPOSITE BINARY STATE, MEANS CONNECTING SAID READOUT MEANS OF EACH SAID STORAGE MEANS AFTER THE FIRST STORAGE MEANS IN EACH SAID COLUMN TO SAID FIRST OUTPUT LINE OF THE PRECEDING STORAGE MEANS IN THE SAME COLUMN, AN M ORDER BINARY ACCUMULATOR ARRANGED IN SAID M COLUMNS, EACH SAID ORDER OPERABLE TO STORE A FIRST BINARY DIGIT IN A FIRST STORAGE ELEMENT, TO RECEIVE A SECOND BINARY DIGIT IN A SECOND STORAGE ELEMENT, TO ADD SAID FIRST AND SECOND BINARY DIGITS STORING THE BINARY SUM IN A THIRD STORAGE ELEMENT AND PROPAGATING A BINARY DIGIT CARRY IN ACCORDANCE WITH SAID SUM, MEANS COMMON CONNECTING SAID SECOND OUTPUT LINES OF ALL SAID STORAGE MEANS IN EACH SAID COLUMN TO AN INPUT TERMINAL OF SAID SECOND STORAGE ELEMENT OF A CORRESPONDING ORDER OF SAID ACCUMULATOR WHEREBY EACH SIGNAL ON SAID COMMON CONNECTING MEANS ENTERS A COUNT IN THE CORRESPONDING ORDER OF SAID ACCUMULATOR,BINARY CARRY REGISTERS CORRESPONDING TO EACH ORDER OF SAID ACCUMULATOR, EACH SAID CARRY REGISTER ARRANGED IN SAID COLUMN CORRESPONDING TO THE NEXT HIGHER ORDER 